Field of the Invention
This invention relates to the field of hybrid devices, and more particularly to low thermal stress hybrid device packages.
Description of the Related Art
A hybrid device is an electronic component which typically includes two or more distinct electronic components, such as integrated circuits (ICs), housed within a common package. One example is a detector array device, which would typically include a detector array IC and a readout IC (ROIC), housed in a common package which provides an electrical interface to the ICs.
The various components making up a hybrid device package typically have different coefficients of thermal expansion (CTEs). A hybrid device such as a detector array is generally operated at a very low operating temperature. Thus, as the device is cooled from room temperature to operating temperature, the result is thermal stress. If the stresses are unbalanced, the structure may ‘bow’. Bowing is undesirable for an optical sensor because it causes the sensor elements to deviate from a perfect plane, thus making it more difficult to precisely focus an optical image on the sensor. Bowing also produces large shear strains in the detector array IC, which facilitates defect nucleation and growth which degrade detector performance.
There is typically a substantial mismatch between the CTE of the detector and the ROIC, with the detector having a higher CTE than the ROIC. If this is not mitigated, then upon cooling the detector is under tensile stress, and ‘channel cracking’ can occur which can significantly degrade device performance. This tends to occur at temperatures below which the energy released in the mechanical relaxation of the stressed film is greater than the surface energy of the newly-formed crack surface.
One possible hybrid device package embodiment is shown in FIG. 1. The package 10 includes an IC 12, such as a detector array IC (or simply, “detector”), mounted on a readout IC (ROIC) 14, which is in turn mounted on a “balanced composite structure” (BCS) 16 which includes a balancing layer 18 and a compressive layer 20. The BCS is mounted to a baseplate 22, to which an electrical interface board 24 is also mounted. Electrical connections between ROIC 14 and board 24 would typically be effected with wire bonds 26.
In an effort to reduce thermal stresses, the CTE values of baseplate 22 (suitably molybdenum), BCS/ROIC stack 16/14 and IC 12 are preferably matched. This reduces the stress on the detector by compressing the ROIC to match the thermal contraction of the detector. However, the CTE of electrical interface board 24, typically made from a ceramic or polymer material, is likely to be different from that of the baseplate, BCS and IC 12. This mismatch can lead to stress on and/or the bowing of the device structure (if board 24 and baseplate 22 are rigidly bonded together), or relative motion between the board and the baseplate (if the board is mounted to the baseplate such that it can move with respect to the baseplate) as the device is cooled.
Another possible hybrid device package is shown in FIG. 2. Here, the package 30 includes an IC 32 such as a detector array IC. In this example, IC 32 has had its substrate removed and is mounted on a readout IC (ROIC) 34, which is in turn mounted on a baseplate 36, suitably silicon carbide (SiC) or Invar. An electrical interface board 38 is also mounted on baseplate 36, with electrical connections between the ROIC and board typically effected with wire bonds 40.
In this design the CTE of baseplate 36 is preferably matched to that of ROIC 34, which reduces the stress on the ROIC. However, all the thermal mismatch stress is then concentrated in the thin detector film. Since the detector layer is much thinner than the ROIC and substrate there is very little bowing, but the high tensile stress can result in channel cracking of the detector. The CTE of the baseplate is also likely to be different from that of the electrical interface board 38, which can lead to bowing of the assembly.